Field of the Invention
Embodiments of the present invention relate generally to integrated circuit design and, more specifically, to a mixed threshold flip-flop element to mitigate hold time penalty due to clock distortion.
Description of the Related Art
In the field of integrated circuit technology, bi-stable multivibrators, commonly referred to as flip-flop elements, are widely deployed to implement various functions. In particular, flip-flop elements deployed in graphics processing units (GPUs) implement functions such as data storage, data transfer, counters, and frequency division. A flip-flop element has two stable states and stores or transfers data by latching the state of the input data and transmitting the latched state to the output.
Flip-flop elements are constructed using transistors, typically field-effect transistors, integrated onto a substrate, such as silicon. A periodic signal, referred to as a clock signal, is applied to one input of the flip-flop element in order to store the state of a second signal, referred to as a data input signal. The latching action of the flip-flop element may occur on the rising edge of the clock, on the falling edge, or in the case of double data rate systems, on both edges. The flip-flop element then presents the stored state of the input signal at the output of the flip-flop element. In order to reliably store the data input, the data input signal is held stable for a minimum amount of time prior to the active edge of the clock signal (the setup time) and a minimum amount of time after the active edge of the clock signal (the hold time). Otherwise, the flip-flop element may not correctly transfer the state of the data input signal. Thus, the integrity of the relationship between the data input and the clock input is critical to proper timing within the system.
A trend toward faster, smaller, more power-efficient computer systems has led to the development of new transistor technologies in order to achieve higher performance and higher circuit density while maintaining low power consumption. Specifically, a critical design criterion is increasing performance per Watt. A key development in this trend is a type of transistor termed a FinFET. A FinFET is a multi-gate three-dimensional field-effect transistor (FET) that offers significant performance improvement and power reduction compared to conventional planar complementary metal-oxide-semiconductor (CMOS) devices. FinFETs have a three-dimensional structure, providing the ability to achieve a higher transistor density per square area relative to planar FETs. Further, the FinFET can operate at a lower voltage for a given leakage current. Because of these advantages, FinFETs are an attractive technology to implement flip-flop elements and provide increased density, performance, and power efficiency.
One drawback of FinFET technology is that the Miller capacitance in a FinFET is typically higher relative to conventional CMOS structures. The Miller effect is the increase in input capacitance of an inverting amplifier, such as an FET, due to the amplification of the capacitance between the input and output terminals. One effect of the increased Miller capacitance caused by the Miller effect is a distortion of a signal at the gate terminal of a FinFET, leading to an increase in the rise time of the gate waveform. This distortion causes an uncertainty in the point at which the input data transfers to the output, of the FinFET. The variation in the actual trip threshold causes a delay in the clock signal. This delay further increases with loading (that is, increased fan-out), lower temperature operation, and lower voltage operation. As a result, the hold time with respect to the data input of a flip-flop element increases in order to accommodate the longer clock signal delay. The increased hold time limits the attainable speed of system processing, leading to reduced system performance.
As the foregoing illustrates, what is needed in the art is a more effective technique to increase performance in flip-flop element design.